1. Field of the Invention
The present invention generally relates to a PLL (Phase-Locked Loop) circuit used for communication equipment, and more particularly, to a PLL circuit suitable for being implemented as a semiconductor integrated circuit.
2. Description of the Prior Art
The prior art pertinent to the present invention is found in R. Cordell, et al., "A 50 MHz Phase-and Frequency-Locked Loop" IEEE Journal of Solid-State Circuits, SC-14, No. 6, pp. 1003-1010, December 1979 (U.S.A.). A detailed description of the prior art will be given below, making reference to the related drawings.
FIG. 2 shows an example of a conventional PLL circuit. The PLL circuit comprising an integrated circuit has an input terminal 1 for an input signal Vi. The input terminal 1 is connected to a signal adder 4 through a phase comparator 2 and a frequency difference detector 3. The phase comparator 2 is a circuit which transmits a phase difference signal S2 after detecting a phase difference between the input signal Vi and an oscillating signal S6, while the frequency difference detector 3 is a circuit which transmits a frequency difference signal S3 after detecting a frequency difference between the input signal Vi and the oscillating signal S6. Further, the signal adder 4 is a circuit which transmits to a loop filter 5 an added, resultant signal S4 obtained by adding the phase difference signal S2 and the frequency difference signal S3. The loop filter 5 is a circuit which transmits a control signal S5 having a low frequency after removing a high frequency constituent from the added signal S4. The loop filter 5 has an output port connected to a voltage-controlled oscillator 6. The voltage-controlled oscillator 6 is a circuit which transmits the oscillating signal S6 having an oscillating frequency which varies in response to the control signal S5. The phase comparator 2 and the frequency difference detector 3 are connected to the output terminal of the voltage-controlled oscillator.
A phase-locked loop R comprising the phase comparator 2, the signal adder 4, the loop filter 5, and the voltage-controlled oscillator 6 has a capture range (a frequency range for the input signal Vi which is captured by the phase synchronous loop R) .DELTA.F which is determined according to a type of each circuit configuration or a time constant of the loop filter 5.
The operations of the PLL circuit are described below.
To begin with, a level of the phase difference signal S2 is zero and the voltage-controlled oscillator 6 oscillates with its specific oscillating frequency (a free-running frequency) when the input signal Vi has not been fed to the PLL circuit. Supposing that the frequency of the input signal Vi is out of the capture range .DELTA.F, the frequency difference detector 3 outputs the frequency difference signal S3. As the frequency difference signal S3 is fed to the voltage-controlled oscillator 6 in the form of the control signal S5 through the signal adder 4 and the loop filter 5, the oscillating frequency generated from the voltage-controlled oscillator 6 becomes close to the frequency of the input signal Vi. Then, the frequency difference detector 3 stops transmitting the frequency difference signal S3, and on the contrary, the phase difference signal S2 is produced from the phase comparator 2. The phase difference signal S2 is fed to the voltage-controlled oscillator 6 in the form of the control signal S5 through the signal adder 4 and the loop filter 5 so that the phase of the output signal Vo of the voltage-controlled oscillator 6 can be locked to the phase of the input signal Vi.
The PLL circuit shown in FIG. 2 is generally used for extracting a clock signal and has a function for extracting only a desired frequency constituent from the input signal Vi including noise.
When the PLL circuit is used as a noise filter, for example, it is necessary to take a noise bandwidth into consideration. The noise bandwidth is generally a frequency bandwidth which extends to only 3 dB from the maximum attenuation rate in terms of the relationship between frequency and attenuation rate. In order to highten the function of the PLL circuit as a noise filter, it is necessary to set the noise bandwidth narrow by increasing a time constant of the loop filter 5. If this is done so, however, a capture range determined by the time constant of the loop filter 5 also becomes narrow.
FIG. 2 shows an ordinary PLL circuit consisting of only a phase synchronous loop R, in which the frequency difference detector 3 is provided for widening the capture range so that the PLL circuit can receive the input signal Vi having a frequency range as wide as the widened capture range.
Even in the PLL circuit having the above-mentioned configuration, however, the capture range can be widened only a few percent. In order to operate the PLL circuit, it is necessary to set the free-running frequency of the voltage-controlled oscillator 6 within the capture range, and therefore, further improvement in accuracy of the voltage-controlled oscillator is necessary. Consequently, it was impossible to constitute the voltage-controlled oscillator 6 by incorporating only a simply structured and inexpensive voltage-controlled oscillating circuit suitable for an integrated circuit, and it was necessary to incorporate circuit elements, such as inductors, capacitors, etc., as external components. This caused an increase in the quantity of elements used in a circuit and the space required for setting up a circuit, resulting in a hindrance in the speed-up of operations as well as an increase in cost.